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ISL90810
Single Digitally Controlled Potentiometer (XDCPTM)
Data Sheet November 10, 2006 FN8234.2
Low Noise/Low Power/I2C Bus/256 Taps
The ISL90810 integrates a digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated Wiper Register (WR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. When powered on the ISL90810's wiper will always commence at mid-scale (128 tap position). The DCP can be used as three-terminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* 256 resistor taps - 0.4% resolution * I2C serial interface with write/read capability * Power-on preset to mid-scale (128 tap position) * Wiper resistance: 70 typical @ 3.3V * Standby current 5A max * Power supply: 2.7V to 5.5V * 50k, 10k total resistance * 8 Ld MSOP * Pb-free plus anneal available (RoHS compliant)
Pinout
ISL90810 (8 LD MSOP) TOP VIEW
NC SCL SDA GND 1 2 3 4 8 7 6 5 VCC RH RL RW
Ordering Information
PART NUMBER ISL90810WIU8 ISL90810WIU8Z* (Note) ISL90810WAU8Z* (Note) ISL90810UIU8 ISL90810UIU8Z* (Note) ISL90810UAU8Z* (Note) PART MARKING AJL DEN 810WA AJK DEM 810UA RTOTAL (k) 10 10 10 50 50 50 TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +105 -40 to +85 -40 to +85 -40 to +105 PACKAGE 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP (Pb-free) PKG. DWG# M8.118 M8.118 M8.118 M8.118 M8.118 M8.118
*Add "-TK" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL90810 Block Diagram
VCC
RH
SDA
I2C AND CONTROL
WIPER REGISTER
SCL
RL RW
GND
Pin Descriptions
MSOP PIN 1 2 3 4 5 6 7 8 SYMBOL NC SCL SDA GND RW RL RH VCC DESCRIPTION No connection I2C interface clock Serial data I/O for the I2C interface Ground "Wiper" terminal of the DCP "Low" terminal of the DCP "High" terminal of the DCP Power supply
Equivalent Circuitry
RTOTAL RH CH 10pF CW 25pF RW CL 10pF RL
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FN8234.2 November 10, 2006
ISL90810
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at Any Digital Interface Pin With Respect to VSS . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at Any DCP Pin With Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +105C ESD HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Thermal Information
Thermal Resistance (Typical, Note 1) 8 Ld MSOP Package JA (C/W) 130
Maximum Junction Temperature (Plastic Package . . . . . . . . +150C
Recommended Operating Conditions
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Automotive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +105C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL RTOTAL RW CH/CL/CW ILkgDCP INL (Note 7) DNL (Note 6)
Over recommended operating conditions unless otherwise stated. PARAMETER TEST CONDITIONS W, U versions respectively -20 VCC = 3.3V @ +25C Wiper current = VCC/RTOTAL 70 10/10/25 Voltage at pin from GND to VCC -1 Monotonic over all tap positions W option -0.75 U option -0.5 0 0 -7 -2 1 0.5 -1 -0.5 4 0.1 1 MIN TYP (Notes 2) 10, 50 +20 200 MAX UNIT k % pF A
RH to RL Resistance RH to RL Resistance Tolerance Wiper resistance Potentiometer Capacitance (Note 14, Equivalent circuitry) Leakage on DCP pins (Note 14)
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) Integral Non-Linearity Differential Non-Linearity 1 +0.75 +0.5 7 2 0 0 ppm/C LSB (Note 3) LSB (Note 3) LSB (Note 3) LSB (Note 3) LSB (Note 3)
ZSerror (Note 4) Zero-Scale Error
W option U option
FSerror (Note 5) Full-Scale Error
W option U option
TCV (Notes 8, 14) Ratiometric Temperature Coefficient DCP Register set to 80 hex RINL (Note 12) RDNL (Note 6) Integral Non-Linearity Differential Non-Linearity DCP register set between 20 hex and FF hex. Monotonic over all tap positions -1
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) 1 +0.75 +0.5 1 0.5 35 7 2 MI (Note 9) MI (Note 9) MI (Note 9) MI (Note 9) MI (Note 9) ppm/C
DCP register set between 20 hex W option -0.75 and FF hex. Monotonic over all tap U option -0.5 positions W option U option 0 0
Roffset (Note 10) Offset
TCR (Notes 13, 14)
Resistance Temperature Coefficient DCP register set between 20 hex and FF hex
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FN8234.2 November 10, 2006
ISL90810
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 ISB PARAMETER VCC Supply Current (Volatile Write/Read) VCC Current (Standby) TEST CONDITIONS fSCL = 400kHz; SDA = Open; (for I2C, Active, Read and Volatile Write States only) VCC = +5.5V, I2C Interface in Standby State, Temperature range from -40C to +85C VCC = +5.5V, I2C Interface in Standby State, Temperature range from -40C to +105C VCC = +3.6V, I2C Interface in Standby State, Temperature range from -40C to +85C VCC = +3.6V, I2C Interface in Standby State, Temperature range from -40C to +105C ILkgDig Leakage Current at Pins SDA and SCL Voltage at pin from GND to VCC SCL falling edge of last bit of DCP Data Byte to wiper change Minimum VCC at which memory recall occurs 1.8 0.2 VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state 3 -10 2 2 0.8 0.8 5 8 2 5 10 1 2.6 A A A A A s V V/ms ms MIN TYP (Note 1) 20 MAX 100 UNITS A
tDCP (Note 14) DCP Wiper Response Time Vpor VCCRamp tD (Note 14) Power-On Recall Voltage VCC Ramp Rate Power-Up Delay
SERIAL INTERFACE SPECIFICATIONS VIL VIH Hysteresis (Note 14) SDA, and SCL Input Buffer LOW Voltage SDA, and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis -0.3 0.7*VCC 0.05* VCC 0 0.4 10 400 Any pulse narrower than the max spec is suppressed. 50 900 1300 0.3*VCC VCC+0.3 V V V V pF kHz ns ns ns
VOL (Note 14) SDA Output Buffer LOW Voltage, Sinking 4mA Cpin (Note 14) SDA, and SCL Pin Capacitance fSCL tIN (Note 14) tAA (Note 14) SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until SDA Valid exits the 30% to 70% of VCC window.
tBUF (Note 14) Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition. tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Input Data Setup Time Input Data Hold Time STOP Condition Setup Time Measured at the 30% of VCC crossing. Measured at the 70% of VCC crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VCC. From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC.
1300 600 600 600 100 0 600
ns ns ns ns ns ns ns
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FN8234.2 November 10, 2006
ISL90810
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL tHD:STO tDH (Note 14) tR (Note 14) tF (Note 14) Cb (Note 14) PARAMETER TEST CONDITIONS MIN 600 0 20 + 0.1 * Cb 20 + 0.1 * Cb 10 1 250 250 400 TYP (Note 1) MAX UNITS ns ns ns ns pF k
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge. Both or Volatile Only Write crossing 70% of VCC. Output Data Hold Time SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window. From 30% to 70% of VCC From 70% to 30% of VCC Total on-chip and off-chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5k. For Cb = 40pF, max is about 15~20k
Rpu (Note 14) SDA and SCL Bus Pull-Up Resistor Off-Chip
SDA vs SCL Timing
tF tHIGH tLOW tR
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
NOTES: 2. Typical values are for TA = +25C and 3.3V supply voltage. 3. LSB: [V(RW)255 - V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 4. ZS error = V(RW)0/LSB. 5. FS error = [V(RW)255 - VCC]/LSB. 6. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 7. INL = (V(RW)i - i * LSB - V(RW)0)/LSB, for i = 1 to 255. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 8. TC V = --------------------------------------------------------------------------------------------- x ---------------- for i = 16 to 240 decimal, T = -40C to +105C. Max( ) is the maximum value of the wiper [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 145C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 9. MI = |R255 - R0|/255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. Roffset = R0/MI, when measuring between RW and RL. 10. Roffset = R255/MI, when measuring between RW and RH. 11. RDNL = (Ri - Ri-1)/MI, for i = 32 to 255. 12. RINL = [Ri - (MI * i) - R0]/MI, for i = 32 to 255. [ Max ( Ri ) - Min ( Ri ) ] 10 13. TC R = --------------------------------------------------------------- x ---------------- for i = 32 to 255, T = -40C to +105C. Max( ) is the maximum value of the resistance and Min ( ) is the [ Max ( Ri ) + Min ( Ri ) ] 2 145C minimum value of the resistance over the temperature range. 14. This parameter is not 100% tested.
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FN8234.2 November 10, 2006
ISL90810 Typical Performance Curves
160 Vcc = 2.7, T = +85C 140 WIPER RESISTANCE () 120 100 80 60 40 20 0 0 50 100 150 200 250 TAP POSITION (DECIMAL) Vcc = 5.5, T = -40C Vcc = 5.5, T = +85C Vcc = 5.5, T = +25C STANDBY ICC (A) Vcc = 2.7, T = -40C Vcc = 2.7, T = +25C 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.7 3.2 +25C 3.7 4.2 VCC (V) 4.7 5.2 +85C -40C
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [I(RW) = VCC/Rtotal] FOR 50k (U)
0.2 0.15 0.1 DNL (LSB) 0.05 0 -0.05 -0.1 -0.15 -0.2 0 Vcc = 5.5, T = +25C Vcc = 2.7, T = +85C Vcc = 5.5, T = +85C INL (LSB) 0.1 0 -0.1 -0.2 -0.3 Vcc = 5.5, T = -40C Vcc = 2.7, T = +25C 0.3 Vcc = 2.7, T = -40C 0.2
FIGURE 2. STANDBY ICC vs VCC
Vcc = 2.7, T = -40C Vcc = 5.5, T = -40C
Vcc = 5.5, T = +85C
Vcc = 2.7, T = +25C Vcc = 2.7, T = +85C Vcc = 5.5, T = +25C
50
100
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
0.4
0 -0.1
0.35 ZSerror (LSB) FSerror (LSB)
-0.2 -0.3
Vcc = 5.5V
0.3 2.7V 0.25
-0.4 -0.5 -0.6 -0.7 Vcc = 2.7V
0.2
5.5V
-0.8 -0.9
0.15 -40
-20
0
20
40
60
80
-1 -40
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. ZSerror vs TEMPERATURE
FIGURE 6. FSerror vs TEMPERATURE
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FN8234.2 November 10, 2006
ISL90810 Typical Performance Curves
0.3 Vcc = 2.7, T = +25C 0.2 0.1 DNL (LSB) INL (LSB) 0 -0.1 Vcc = 5.5, T = +85C -0.2 -0.3 32 Vcc = 2.7, T = +85C Vcc = 2.7, T = -40C Vcc = 5.5, T = -40C 232 Vcc = 5.5, T = +25C
(Continued)
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 Vcc = 2.7, T = +85C Vcc = 5.5, T = +25C -0.5 32 82 132 Vcc = 2.7, T = -40C 182 232 Vcc = 5.5, T = -40C Vcc = 5.5, T = +85C Vcc = 2.7, T = +25C
82
132 182 TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 50k (U)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 50k (U)
1.50 END TO END RTOTAL CHANGE (%) 1.00
20
10 0.50 0.00 5.5V TC (ppm/C) 0 20 40 60 80 2.7V
0
-0.50 -1.00 -1.50 -40
-10
-20
-20 32
82
132
182
232
TEMPERATURE (C)
TAP POSITION (DECIMAL)
FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
35 25 15 TC (ppm/C) 5 OUTPUT -5 -15 -25 32 INPUT
Tap Position = Mid Point RTOTAL = 9.4K 57 82 107 132 157 182 207 232
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (2.2MHz)
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FN8234.2 November 10, 2006
ISL90810 Typical Performance Curves
Signal at Wiper (Wiper Unloaded)
(Continued)
SCL
Signal at Wiper (Wiper Unloaded Movement From ffh to 00h)
Wiper Movement Mid Point From 80h to 7fh
FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)
FIGURE 14. LARGE SIGNAL SETTLING TIME
Principles of Operation
The ISL90810 is an integrated circuit incorporating one DCP with its associated registers, and an I2C serial interface providing direct communication between a host and the potentiometer.
I2C Serial Interface
The ISL90810 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL90810 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of the DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). When the WR of the DCP contains all zeroes (WR[7:0]: 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR of the DCP contains all ones (WR[7:0]: FFh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (0 decimal) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL90810 is being powered up, The WR is reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. The WR can be read or written to directly using the I2C serial interface as described in the following sections. The I2C interface Address Byte has to be set to 00hex to access the WR.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 15). On power-up of the ISL90810 the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL90810 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 15). A START condition is ignored during the powerup for the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 15) A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 16).
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FN8234.2 November 10, 2006
ISL90810
The ISL90810 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL90810 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 0101000 as the seven MSBs. The LSB is the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation (See Table 1) The address byte is set to 00h and follows the identification byte. Read and write operations always point to address 00h, indicating the WR for the device.
TABLE 1. IDENTIFICATION BYTE FORMAT 0 (MSB) 1 0 1 0 0 0 R/W (LSB)
Data Protection
A valid Identification Byte. Address Byte, and total number of SCL pulses act as a protection for the registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. The Data Byte is transferred to the Wiper Register (WR) at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte.
Read Operation
A Read operation consists of a three byte instruction followed by one Data Byte (See Figure 18). The master initiates the operation issuing the following sequence: a START, the identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL90810 responds with an ACK. The the ISL90810 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a ACK and a STOP condition) following the last bit of the Data Byte (See Figure 18).
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL90810 responds with an ACK. At this time the device enters its standby state (See Figure 17).
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
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FN8234.2 November 10, 2006
ISL90810
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL90810
01 01 0 000 A C K
00000000 A C K A C K
FIGURE 17. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W=0
ADDRESS BYTE
S T A IDENTIFICATION R BYTE WITH T R/W=1
AS CT KO P
SIGNAL AT SDA
01010000 A C K
000000 00 A C K
01010001 A C K
SIGNALS FROM THE SLAVE
DATA BYTE
FIGURE 18. READ SEQUENCE
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FN8234.2 November 10, 2006
ISL90810 Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 4.75 0.40 8 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 2 01/03
MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116 0.187 0.016 8 0.003 0.003 5o 0o
MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120 0.199 0.028
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -C-
R1 R
b c D E1
A
A2
4X
L L1
e E L L1 N R
0.026 BSC
0.65 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1 0
SIDE VIEW
15o 6o
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN8234.2 November 10, 2006

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